KSZ9031RNXCC-Microchip

Descripción

The KSZ9031RNXCC interface chip is designed and developed by Microchip, una empresa de semiconductores de renombre mundial. This device has always been the first choice in this type of chip, and is used in various circuits by engineers. The KSZ9031RNXCC device is AEC-Q100 compliant and meets various applications in the automotive field. xt-shenzhen can provide global customers with other original Microchip semiconductor devices including KSZ9031RNXCC model. xt-shenzhen welcome global customers to contact us anytime! ! !

los KSZ9031RNXCC is a single chip for IEEE 802.3 applications with programming options for external delays and adjustments and corrections for TX and RX timing paths. Power-down mode with energy detection reduces power consumption when the device is not connected to the cable. Adopt 48-pin QFN package to expand the application field, mainly used in laser/network printers, Network Attached Storage (NAS), Network Servers, Gigabit LAN on Motherboard (GLOM), Broadband Gateways, Gigabit SOHO/SMB Routers, IPTV, IP Set-Top Boxes, Game Consoles and other consumer electronics applications.

• RGMII timing supports RGMII version 2.0 compliant on-chip latency,
• RGMII with 3.3V/2.5V/1.8V Tolerant I/O
• Auto-negotiation to automatically select the highest link speed (10/100/1000 mbps) and duplex (half/full)
• On-chip LDO controller supports single 3.3V supply operation – requires only one external FET to generate 1.2V for core
• Jumbo frame support up to 16 KB
• 125 MHz reference clock output
• Wake-on-LAN (WOL) support with powerful custom packet inspection
• AEC-Q100 qualified for automotive applications
• Programmable LED outputs for link, activity and speed
• Li nkMD TDR-based cable diagnostics to identify faulty copper cabling
• Parametric NAND tree support detects faults between chip I/O and board
• Loopback mode for diagnostics
• Automatic MDI/MDI-X crossover detects and corrects pair swaps at all operating speeds
• Automatic detection and correction of pair swaps, pair skew and pair polarity
• MDC/MDIO management interface for PHY register configuration
• Interrupt pin option
• Power down and power saving mode
• Operating voltage – Centro (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator) – VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V – Transceiver (AVDDH): 3.3V or 2.5V (commercial temperature)