Оригинальный чип DSPIC33EP512MU810-I/PT

Описание

The DSPIC33EP512MU810-I/PT device is a very popular microcontroller (MCU) in the market. It adopts a lot of low power consumption designs, which greatly reduces the energy consumption of the equipment. Because of its excellent performance, it has been in short supply. With years of accumulation, xt-shenzhen can efficiently complete the procurement plan for global manufacturer customers! ! !

The DSPIC33EP512MU810-I/PT digital signal controller provides DSP performance. The device core is designed to implement digital filtering algorithms, high-speed precision digital control loops, digital audio and speech processing. With motor control peripherals, it provides support for the design of high-performance, precision motor control systems. Specially designed on-chip peripherals are provided to ensure high-performance digital power.

• Code efficient (C and assembly) architecture
• Single cycle (MAC/MPY) with dual data fetch
• Single-cycle mixed-sign MUL plus hardware divide
• 32-bit multiplication supports clock management
• 2% Internal Oscillator
• Programmable PLL and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Fast wake-up and start-up power management
• Integrated power-on reset and brown-out reset
• Up to seven PWM pairs with independent timing
• Dead time for rising and falling edges
• 8.32 ns PWM resolution
• Programmable fault input
• Flexible trigger configuration Advanced analog features for ADC conversions
• Peripheral Pin Select (PPS) to allow function remapping
• Real-time clock and calendar (RTCC) module communication interface
• USB 2.0 OTG Compatible Full Speed Interface
• Data converter interface (DCI) module with support for I2S and audio codecs
• PPS allows function remapping
• Parallel Master Port (PMP)
• Programmable Cyclic Redundancy Check (CRC) Direct Memory Access (DMA)
• Selectable open-drain, pull-up and pull-down
• External interrupt authentication and Class B support on all I/O pins
• ИИЭР 1149.2 compliant e (JTAG) boundary scan